Thoughts on Core Integration and Test

In just a few years, cores have become an integral part of the design process for system-on-a-chip products. It is not hard to see why; today’s gate capacities in the millions are well beyond the capabilities of most design teams. The effective use of such large capacities suggests, even demands, the ability to reuse existing designs. Some companies have developed effective techniques and processes to reuse designs developed in-house. However, a fairly large commercial industry has arisen to provide reusable cores to external customers. Such cores may be available in sythesizable RTL form, gate-level netlist form, or layout-level “hard macro” form. Each method of core delivery has implications for both the core provider and the core user.